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(30 hours) CÔNG NGHỆ VI ĐiỆN TỬ(Microelectronic Technology) Chương 8: Basic Design  Nội dung Concepts Multiplexers Encoders Priority Encoders Decoders Comparators BCD to 7 SEGMENT ALUs Module General definition module module_name ( port_list ); port declarations; … variable declaration; … description of behavior endmodule Example module HalfAdder (A, B, Sum Carry); input A, B; output Sum, Carry; assign Sum = A ^ B; //^ denotes XOR assign Carry = A & B; // & denotes AND endmodule Description Styles Structural: Logic is described in terms of Verilog gate primitives Execution: Concurrent Example: not n1(sel_n, sel); and a1(sel_b, b, sel_b); and a2(sel_a, a, sel); or o1(out, sel_b, sel_a); Description Styles (cont) Dataflow: Specify output signals in terms of input signals Uses continuous assignment statement Format: assign net = expression; All continuous assignment statements execute concurrently Order of the statement does not impact the design Example: assign out = (sel & a) | (~sel & b); Description Styles (cont.) Behavioral: Algorithmically specify the behavior of the design Example: if (select == 0) begin out = b; end else if (select == 1) begin out = a; end Behavioral Modeling (cont.) always statement : Sequential Block Sequential Block: All statements within the block are executed sequentially When is it executed? Occurrence of an event in the sensitivity list Event: Change in the logical value Statements with a Sequential Block: Procedural Assignments Procedural Constructs Two Procedural Constructs initial Statement always Statement initial Statement : Executes only once always Statement : Executes in a loop Example: … initial begin Sum = 0; Carry = 0; end … … always @(A or B) begin Sum = A ^ B; Carry = A & B; end … Event Control Combinational Logic Combination logic function can be expressed as: logic_output(t) = f(logic_inputs(t)) Combinational logic can be implemented with concurrent and sequential statements. Concurrent statements are used in dataflow and structural descriptions. Sequential statements are used in behavioral descriptions. Concurrent statements vs Sequential statements MUX 2-1 module mux2to1 (m, x, y, s); input x, y, s; output m; wire m; assign m = (~s & x) | (s & y); endmodule Strutural/gate level Data flow MUX 2-1 Behavior System Tasks Display tasks $display : Displays the entire list at the time when statement is encountered $monitor : Whenever there is a change in any argument, displays the entire list at end of time step Simulation Control Task $finish : makes the simulator to exit $stop : suspends the simulation Time $time: gives the simulation Test Bench Simulation Results MUX 4-1 MUX 4-1 MUX 4-1 Simulation Results MUX 4-1 8-bit width Multiplexer Conditional Operator 8-bit width Multiplexer CASE Statement if .. else Statement 8-bit width Multiplexer HALFADDER (HA) FULL ADDER (FA) 4-BIT FULL ADDER 4-BIT FULL ADDER Simulation Results 3-8 DECODER 2 -4 DECODER WITH EN 8-3 Encoder 4-2 Encoder with EN I1 I2 EN I3 I0 Y0 Y1 2x4 Decoder 8- LEVEL PRIORITY ENCODER 8- LEVEL PRIORITY ENCODER BCD to 7 SEGMENT ALU A B Cin Sel Y 8 8 4 8 ALU ALU ALU